1. Field of the Invention
The invention relates to a floating gate and more particularly to a floating gate with tip of a stack gate vertical memory and a fabricating method thereof.
2. Description of the Related Art
Memory devices for non-volatile storage of information are currently in widespread use, in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
An advantage of EPROM is that it is electrically programmed, but for erasing, EPROM requires exposure to ultraviolet (UV) light.
In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device.
EEPROM devices have the advantage of electrical programming and erasing, achieved by charging and discharging actions controlled by the control gate. The actions also affect the conductivity of the channel between source and drain.
One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, memory erasure is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. Another advantage of flash memory is low power consumption.
FIGS. 1a to 1c are cross-sections of the conventional method for forming a stack gate with tip vertical memory. FIG. 1a is a top view, FIG. 1b is a cross section of line XX in FIG. 1a, and FIG. 1c is a cross section of line YY in FIG. 1a. 
A semiconductor substrate, such as a silicon substrate, 10 is provided, a drain area 101, such as an ion doped area, a source area 102, such as an ion doped area, a gate dielectric layer 11, such as a gate oxide layer, a conducting layer 12, such as a polysilicon layer or an epi-silicon layer, as a floating gate, a conducting layer 13, such as a polysilicon layer or an epi-silicon layer, as a control gate, a contact 14, such as a Cu layer, for connecting the source 102, a metal layer 15, such as a Cu layer, for connecting the drain area 101, a isolation area 16, such as an STI, and a liner layer 17, such as a liner oxide layer, in the isolation layer 16 are sequentially formed thereon.
When the edge of the floating gate is a tip, the electrical field is easily concentrated, and the point is easily discharged. If the point discharge is increased, the effects of erasure increase.
In addition, the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture.